Seoul and SEALSQ Partner to Establish Post-Quantum Chip Security Center Seoul and SEALSQ co-develop a research center to embed PQC roots of trust into silicon, addressing hardware-level quantum risks.

TL;DR

The Metropolitan Government of Seoul has partnered with semiconductor and cybersecurity provider SEALSQ Corp to establish a dedicated research center focused on hardware-level post-quantum cryptography (PQC). The joint center will research methods for embedding quantum-resistant cryptographic primitives directly into silicon hardware, addressing vulnerabilities at the root-of-trust level before cryptanalytically relevant quantum computers (CRQCs) become operational.

Anchoring PQC in Silicon Hardware

While software-level PQC migration is progressing across enterprise protocol stacks, securing the underlying microarchitectural layer remains a critical bottleneck. Purely software-based PQC implementations lack physical isolation and remain vulnerable to side-channel analysis, differential power analysis, and fault injection attacks.

The Seoul-SEALSQ facility will focus on integrating NIST-standardized lattice-based algorithms—including ML-KEM (FIPS 203) and ML-DSA (FIPS 204)—directly into Secure Elements (SE), Hardware Security Modules (HSMs), and microcontroller units (MCUs). By provisioning post-quantum keys and cryptographic engines into silicon during manufacturing, the facility aims to deliver immutable, hardware-anchored identity and encryption capabilities.

Hardware Lifecycles and Long-Term Quantum Risk

For CTOs and chief information security officers (CISOs), hardware security represents one of the longest lead-time risks in the PQC transition. Unlike application software or web services that can be patched dynamically, hardware roots of trust in edge devices, server motherboards, and industrial control systems often remain in service for 10 to 15 years.

Silicon deployed today using classical RSA or Elliptic Curve Cryptography (ECC) primitives for device authentication or secure boot cannot easily be upgraded if the underlying execution units lack the compute capacity or memory footprint required for lattice-based math. Hardware hardened with native PQC acceleration provides the foundation necessary to prevent future device spoofing, firmware tampering, and retrospective decryption attacks.

Key Takeaways for Security Architecture Teams

The initiative signals a broader industry shift toward silicon-enforced post-quantum security. Enterprise engineering teams preparing for PQC migration should consider the following hardware priorities:

Hardware Inventory & Lifecycle Mapping: Identify hardware security modules, smart cards, and embedded processors that rely on fixed non-agile classical hardware primitives.
Side-Channel Resistance Verification: Evaluate how post-quantum hardware implementations resist physical side-channel attacks, which can present unique vulnerabilities in lattice-based designs.
Vendor Cryptographic Agility Requirements: Require hardware vendors to supply updatable secure execution environments and crypto-agile coprocessors capable of supporting evolving post-quantum standards.